Analog Audio Equalizer

Executive Summary

In this project, I performed the design and layout of an audio equalizer circuit featuring ±9-dB sliders across 4 frequency bands, -12 to 6-dB master volume control, power and clipping indicator LEDs, and power protection features. This involved designing a custom analog system from basic building blocks, with particular attention to signal integrity, power management, component tolerances, and manufacturability. 

Design, tuning, and validation were performed through a mixture of hand calculations, script calculations, and LTspice simulation. Furthermore, Altium Designer was employed to capture a final schematic and layout a 100+ component PCB. Lastly, the bulk of the board was assembled using SMT and through-hole soldering techniques and initial power and signal-path tests were performed.

Overview

Skills: Analog design, PCB design

Tools: Altium designer, LTspice

Design files:

• Schematic v1.4 (.pdf, 1.9 MiB)

• Bill of Materials v1.4 (.xls, 14 KiB)

• Altium PCB Project v1.4 (.zip, 8.5 MiB)

Contents to follow:

• Requirements

• Circuit Design

  • System Overview

  • Power Management

  • Signal Path - Beginning and End

  • Signal Path - Equalizer

• Layout

  • Stackup and DFM Considerations

  • Footprints and Library Management

  • Placement and Routing

• Assembly

• Future Work

• Conclusion

Requirements

The goal of this project was to take concepts I learned throughout my circuits courses and apply them to design something from the ground up.

While there are certainly many layers deeper one could go, I decided to limit my ICs selection to operational amplifiers. I further limited the scope by using a switching power supply adapter and expecting a high-impedance output such as powered speakers.

Some of the other requirements included:

• The device should take and receive signal I/O via 3.5 mm TRS receptacles.

• The device should produce a reasonably flat frequency response within the audible frequency range when sliders are at their center positions.

• The device should not introduce audible noise or distortion to the processed signal.

• The device should allow for the user to amplify or attenuate sound near the musical notes of A1, A3, A5, and A7 (55 Hz, 220 Hz, 880 Hz, and 3520 Hz, respectively) by manipulating sliders.

• The device should have a power switch integrated in a master volume dial and there should be an LED indicator for when the device is on.

• The device should use an indicator LED to indicate when the signal is clipping.

• The device should not be damaged by too high input voltage or too low output impedance.

• The device should be able to withstand reverse polarity of the 5-V power input and function correctly with 150 mV peak-to-peak ripple.

• The device should not draw inrush current larger than 100 mA in the first 100 ms of being plugged in and/or switched on.

Circuit Design

System Overview

The circuit design starts with power management circuitry that provides basic protection and creates a 2.5-V "virtual ground" reference after 5 V are supplied via a 2.1-mm barrel plug. The decision to design the circuit using 5-V single-supply is the result of sticking to the 5-V power supply requirement without adding the complexity of a boost converter and disallowing the use of regulator or charge pump ICs.

Signal input/outputs are taken/provided to the user via 3.5 mm TRS audio receptacles. While the user can provide stereo input, the signal is ultimately processed in mono. This was an acceptable compromise to the client (myself) given the additional complexity stereo would introduce.

After mixing the signal and biasing it at 2.5 V, it goes through a -12 to 6-dB volume control stage. The larger magnitude of attenuation range serves to provide a smooth fade-in as the power switch is integrated in the volume knob. Equalization follows the volume control. Lastly, the processed signal branches to both the audio output and the clipping detector circuit (for the former of which, the 2.5-V biasing is removed).

Power Management

Reverse-Polarity Protection

Reverse-polarity and inrush current protection are implemented with a dual P-type MOSFET, Q1. Q1A acts as a simple reverse-polarity protection circuit by connecting the drain to the power input, the source to the power output, and the gate to ground.

When the polarity is correct, there will be 5 V at the drain. If we assume the FET to be on, that also puts ~5 V at the source, making for a source-to-gate voltage of ~5V. Because this is greater than the absolute value of the threshold voltage (1-3 V), the assumption that the FET is on must be correct. When the polarity is reversed, there will be -5 V at the drain. If we follow the same line of reasoning and assume the FET is on, the source-to-gate voltage would be about -5 V. This being less than the absolute value of the threshold voltage creates a contradiction, meaning that the FET must always be off when polarity is reversed.

Inrush Current Protection

As for inrush current protection, Q1B, along with the C01, C02, and R02, form a soft-start circuit that was designed to draw less than 100 mA when given a 5-V step input in SPICE. The DMP3028LSD was chosen for Q1 because it is a power MOSFET with a relatively low drain-to-source on resistance of 38 mΩ or less. A soft-start circuit was chosen over an NTC thermistor because unlike the latter it would not fail should there be a small time period from when the device is turned off to when it is turned back on again.

Rail Splitter

The rail splitter is a voltage divider followed by a bulk capacitor and buffer. The OPA202 op-amp was chosen for the buffer, as its 35-mA short-circuit current and 25-nF capacitive drive are generous. Furthermore, its offset voltage of 200 μV is more than low enough for the application.

Indicator LEDs

The resistor value for both indicator LEDs were chosen to have a luminous intensity of approximately 7.5 mcd and a viewing angle of 60°, as my research suggested this would make the LEDs to be clearly visible without being unnecessarily bright. The qualitative aspect of this was confirmed in test.

Supply Decoupling

Lastly, it should be mentioned that supply decoupling is performed using 10-μF electrolytic bulk capacitors throughout the board to manage voltage dips and Class 2 ceramic capacitors near ICs to bypass high-frequency noise.

Signal Path - Beginning and End

Signal Path Beginning

The signal path begins with bidirectional TVS diodes. The TSD05C was selected for ESD protection, as it has low leakage and low capacitance. It is reused at the power I/O for simplicity. Following the pull-down resistors, a passive mixer is used to blend left and right channels. A coupling capacitance of approximately 2 μF is used to remove AC bias. Instead of coming after the mixer, this is implemented with the two 1-μF capacitors within the mixer itself.

A 2.5-V DC bias is added to the signal through a 100-kΩ resistor, R13, and C17 serves to filter out high-frequency noise to prevent it from entering the signal path.

Op-Amp Input Protection

The diodes D04 and D05 (BAS116, chosen for low capacitance and leakage) are used to clamp to the 5-V and 0-V references respectively in the case of overvoltage in the signal path. Something important to note is that this clamp allows the signal to go ~0.8 V past the U2A's rails before clamping, whereas the absolute maximum signal input specified in the datasheet is 0.5 V past a given rail.

This relates to two important lessons that I learned regarding IC datasheets. First, I learned that for ICs such as this that already have ESD protection diodes clamping at the input (as is the case for most), exceeding the maximum specified voltage is not what breaks the device, for it is actually exceeding the max current for these diodes that does. For U2A, this is specified to be 10 mA, so the true protection in this signal path comes from the combination of the internal ESD protection diodes and the resistance in the signal path (the 750-Ω resistor, R14 was chosen to limit the current entering U2A to 7.7 mA or less).

The second lesson I learned is that while exceeding an absolute maximum rating was acceptable for a low-liability product such as this, it may not be the case in other contexts. By operating outside of the expected conditions for the device, the potential liability of the manufacturer decreases should something go wrong. Therefore, a tradeoff exists between device cost and long-term financial risk, with the former being prioritized in my design.

So in the same situation, but a different product/industry context, my design decision may have instead been to use precision clamps, for example. This is a solution that adds additional cost (two more op-amps) but would allow the design to follow operating conditions to the datasheet completely. It is also important to clarify that while related to the actual risk of failure and redundant design, this lesson soley pertains to legal risk.

Buffer and Op-Amp Selection

Both the initial buffer whose input protection was just discussed and volume control (U2A and U2B respectively) are implemented with op-amps in the OPA2377 IC. The OPAx377 is the main op-amp used in the signal path throughout the circuit, being also present in the equalizer filters and the other buffers in which the signal passes before reaching the TRS output.

Noise metrics (e.g. voltage/current noise densities measured over similar frequencies) and price were the primary considerations when choosing this op-amp. The OPAx377 was chosen because its specifications were comparable to other op-amps that are known to be suitable for high-quality audio use such as the TL07x and NE553x, while being the cheapest op-amp that was still compatible with the power conditions and signal ranges of the system.

Volume Control

The volume control circuit is a simple inverting configuration with two twists. First, different value resistors surround the potentiometer to give it an uneven amplification/attenuation range of -12 to 6 dB. Second, an additional resistor, R17, is connected from wiper to the amplification end, serving to roughly linearize the volume increase heard by a human ear in response to displacement. This allows for a linear taper potentiometer to be used in place of a less-ubiquitous logarithmic or "audio" taper potentiometer.

Clipping Detector

The secret behind the clipping detector is that it is not a true clipping detector, but instead an approximation of one. First, a comparator takes as input the processed signal (still biased at 2.5 V) and a reference voltage of just under 5 V and outputs high (5 V) when the measured voltage exceeds the reference. In other words, the comparator outputs high just before the signal clips at 5 V.

While it does not check for clipping at 0 V, this still works as an approximation of clipping since audio usually has similar magnitudes on both sides of the time axis. Furthermore, this rough symmetry is enforced when the coupling capacitors in the mixer remove any DC bias from the original signal.

The comparator is followed by a peak detector that extends the pulse and a buffer that ensures there will be sufficient current before driving the indicator LED. The detection threshold (comparator reference voltage) and pulse width are implemented with trimmer potentiometers so they can be tuned if needed. However, by simulating the clipping indicator in LTspice with real audio recordings imported as .wav files, it was found that a detection threshold of 4.75 V (R45 turned 95%) and a pulse duration control (R46) turn of 10% (10-kΩ rheostat value) resulted in the indicator LED staying lit for 10 ms whenever the signal clips.

The TLV9002 was chosen to implement both the comparator and buffer for the clipping detector circuit. In addition to satisfying requirements such as being compatible with the power supply, having a wide input range, and having sufficient current output to drive the LED, it was chosen for its lack of back-to-back diodes protecting input pins. It should be noted that while the datasheet shows a large differential-mode range in the Absolute Maximum Ratings, information regarding its differential-mode range during normal operation and general suitability for comparator use was not clearly explained in the datasheet and instead comes from a statement by an application engineer at TI. While I consider this to be an acceptable source for my needs, I would seek better confirmation in a professional context.

Signal Path End

The end of the signal path is similar to the beginning, containing an coupling capacitor C26 to remove the DC bias, pull-down resistors, and an ESD protection diode. No chassis is assumed to be used, so the TRS receptacles shield pins are connected directly to ground.

Signal Path - Equalizer

Topology

After exploring different options, I decided to use a topology that sums the response of adjustable notch/band boost filters. This circuit is described in literature such as the 1980 National Semiconductor Audio & Radio Handbook (Section 2.17.1, "Ten Band Octave Equalizer", pp. 2-59 thru 2-61) and the July 2001 TI Analog Applications Journal ("An Audio Circuit Collection, Part 3"). This is a flexible topology that allows designers to add as few or many filters as they wish, and provides control over Q factor, center frequency, and attenuation/amplification. Furthermore, gyrators are used in place of real inductors.

The schematic from TI, with component references that will be used in the discussion of design equations to follow is pictured below.

Another important lesson learned through this project was that any engineering literature is susceptible to containing errors. While I primarily used the TI design equations, finding them easier to follow, I also found that they contained a critical error, as their equation for C1 was incorrect. They give C1 as the following:

This equation is wrong because the resistances cancel out, making the units seconds instead of Farads. Rearranging the other design equations provided reveals the correct formula for C1:

Design

A value of Q = 1 was chosen. The design process involved setting the frequency for each stage, then the resistances (controlling the gain), and then calculating rough capacitor values. From there, tuning was performed in SPICE, as the design equations only approximate the circuit's behavior. Furthermore, it was observed that the filter stages are not truly independent, and changing the values of one would change the values of another. Therefore, some back and forth was needed to get to a final theoretical design.

When it came to translating theoretical capacitance values into real components, further simulation was performed to determine the least expensive capacitor values and tolerances that would still result in a similar frequency response. For each capacitor, .step param directives were used to compare different capacitor values. Next, worst-case analysis and Monte Carlo analysis was used to determine the widest resistor and capacitor tolerances that could be used.

Finally, it was found that due to factors such as the small amplification/attenuation range of the filter stage, behavior was roughly linear, making it acceptable to use linear as opposed to S-taper potentiometers.

More About Simulations

To keep this log brief, I'm focusing on explaining design decisions over every simulation performed. However, it's important to note that simulation was used not just for tuning designs but also for verifying that specifications were respected. This included checking things such as total current draw during different phases of operation, current and voltage limits of op-amps, power dissipation of resistors, behavior with low-impedance loads, and frequency response with various different potentiometer displacements.

The following image shows the full amplification/attenuation range of the EQ at each band in isolation. For example:

• The green curve represents frequency response with 55-Hz slider pushed all the way up and all others flat.

• The pink curve represents frequency response with 55-Hz slider pushed all the way down and all others flat.

• The blue curve represents frequency response with 220-Hz slider pushed all the way up and all others flat.

(And so on).

Solid lines represent magnitude and dotted lines represent phase. This was created using the table() function and a custom potentiometer model (available in my LTspice models GitHub repo).

Layout

Stackup and DFM Considerations

A 2-layer PCB with 1 oz copper and a 60-mil FR4 dielectric was designed. By choosing a thicker dielectric, more lateral crosstalk was accepted to achieve better structural integrity given that there are many large through-hole components.

Design rules were chosen to satisfy JLPCB's manufacturing capabilities, while still being conservative, as to not cause problems should a different manufacturer be used. For example, the smallest via size was 0.7 mm pad with 0.3 mm holes, which JLPCB can manufacturer and does not charge extra for. Furthermore, it should be noted that all vias were tented and drill sizes were often reused.

Furthermore, DFM considerations were made with hand and stencil soldering in mind. For example, THT footprints were often created with extra-large pad sizes to make thermal contact with the soldering iron tip easier. Furthermore, while IPC does not recommend a particular corner radius for SMT pads, 0.05 mm was used as it is considered to be an ideal value for applying soldering paste with stencils.

Footprints and Library Management

The library management workflow involved finding components and CAD models, creating or validating footprints, and creating or validating schematic symbols.

Footprints that were created were either made manually or using Altium's wizard and all were validated using mechanical drawings and suggested footprints in datasheets. To better visualize the product, some 3D models for through-hole components were created in Autodesk Fusion and added to the footprint models in Altium, doubling as a sanity check.

During footprint creation and throughout the layout process, guidelines for IPC Class 2 devices (long-term use) and Level B (medium) density components were consulted.

Placement and Routing

Component Placement

As constraints on board size and control location were not present, placement was chosen to minimize net crossovers and board size while still having a straightforward design for the end user.

Track Width

During routing, 15-mil traces were used for signal, 25-mil traces were used for power. While the actual signal current is much lower, the OPAx377 has a maximum short-circuit output current of 50 mA, which corresponds to a minimum trace width of 0.2 mil when designing for a 10 °C rise with 1 oz copper.

Although the minimum trace width manufacturable by JLPCB is 4 mil, 15 mil was chosen for durability reasons given that the board was assembled by hand. While this is not a huge consideration, the lower resistive losses due to the increased conductivity of wider traces is an added benefit for an analog design.

Less than 100 mA of peak current is drawn during startup and up to 60 mA is drawn during normal operation. Performing the same calculation with 100 mA maximum current instead, the minimum trace width is 0.5 mil. Therefore, the choice of 25 mil for power traces is again conservative.

Track Clearance and Crosstalk

A distance of 45 mil or greater was maintained between traces except for small sections at pins and crossovers. This follows the "3x" rule of thumb in PCB design (where distance between traces should be 3 times their width) and meets JLPCB's minimum trace spacing of 4 mil.

However, it does not satisfy the "2H" rule of thumb (where spacing traces a distance 2H for microstrips where H is the dielectric thickness). The 2H rule of thumb pertains to high-frequency signals and is used as a guideline to help keep the field spread sufficiently concentrated to under the low-impedance return path between a trace and a ground plane.

Being an audio-frequency design, this consideration was not important, as factors such as trace-to-trace capacitance and mutual inductance, which are considered in the 3x rule, are what dominate. However, had more time been at my disposal, I would have preferred to follow a more rigorous engineering approach by creating an approximate model of layout parasitics and using SPICE simulation to obtain a quantitative estimate of what I could expect the crosstalk to be, as I did in my Mixed-Signal Testing coursework at McGill.

Copper Pours

As expected, ground was poured on the bottom layer. Less commonly, I did decide to also pour copper on the top. This decision was made in order to further reduce crosstalk and provide a ground plane in places where it is split by a trace. Furthermore, the additional signal-to-ground capacitance that is introduced was considered small enough to not cause an issue given that it is a low-to-medium frequency design.

Grounding

Ground return paths were planned during placement and routing, with transfer vias being used where traces interrupted the bottom-layer plane 

Assembly

To assemble the board, solder paste was first applied with a stencil and most SMT components were soldered on using a hot air rework station in a single pass. The excluded SMT components mostly included 0-Ω resistors, used to separate parts of the circuit so it could be tested incrementally.

This was my first time performing SMT soldering. Although it took several tries to get the stencil right (thankfully I had a pack of disposable lint-free wipes), the joints were quite good. I used an Sn42/Bi58 solder paste. Although I found during an initial test that solder balls were forming, they did not form when I did more preheating.

After performing the main SMT soldering step, every net connected to a component was tested for conductivity with a multimeter to ensure correctness of connections and that no shorts were present.

The next part of assembly involved soldering on the remaining components and performing tests. The power management circuit worked, but U2 unfortunately produced black smoke during a test of the main signal path, excluding the individual EQ filter stages and the clipping detector.

Afterwards, I double-checked to confirm that the net connections were complete and that there were no shorts, so the reason for it breaking was not immediately obvious. This is where I currently am in the project.

Future Work

The next step in development of the device is to return where I left off in assembly by determining what caused U2 to burn, where else damage may have propagated, and seeing what I can do to remedy the issue.

Once the build and initial tests are complete, the plan is to perform characterization and validate requirements. With respect to characterization, a network analyzer will be used to capture the frequency responses with different slider positions. Then, I plan to evaluate metrics relating to SNR and THD with coherent single or multi-tone tests.

Beyond this design, there are several things I would redo if I had the chance in a future revision. However, two things stand out to me as the most critical. Firstly, I would use a high-voltage power supply (or boost the current supply to a higher level) so the system would have a better SNR and amplification/attenuation ranges could be increased without as much fear of clipping.

Secondly, I would like to take a more analytical approach to considerations of noise, crosstalk, distortion, and price. Following rules-of-thumb and rough price/quality points was acceptable in the hobbyist context. However, now that I possess the knowledge to handle these constraints with proper engineering methodology, I should do so.

Conclusion